Multi-node computer system includes multiple central processing unit (CPU) nodes, memory nodes, and input/output (IO) nodes as illustrated in FIG. 7. These CPU nodes, memory nodes, and IO nodes can be coupled together through an interconnect.
The multiple CPU nodes usually connect to an inter-nodes controller to transfer data or message related to various system management tasks. Conventional multi-node computer system usually establishes a direct channel between each CPU node and the inter-nodes controller to control and complete the data transfer. In order to do this, a CPU node in a conventional system uses shared four bytes registers, including a one-byte command register, a one-byte status register, a one-byte data-in register and a one-byte data-out register. However, such hardware configuration wastes hardware resources and causes other implementation problems for a multi-node computer system. For example, conventional CPU nodes use their scratch registers to send or receive data. As a result, the scratch registers in each CPU node may not be available for any other purposes. It is therefore desirable to provide a simple data transfer mechanism for CPU node and the inter-nodes controller in a multi-node computer system that uses minimum hardware resources and eliminates the difficulties encountered in conventional multi-node computer systems.